The present invention generally relates to the design of field effect transistors (FETS) and, more particularly, to a metal oxide silicon (MOS) transistor structure which facilitates mitigation of series resistance and floating body effects.
As is known in the art, transistors such as metal oxide silicon (MOS) transistors, have been formed in isolated regions of a semiconductor body such as an epitaxial layer which was itself formed on a semiconductor, typically bulk silicon, substrate. With an n-channel MOS field effect transistor (FET), the body is of p-type conductivity and the source and drain regions are formed in the p-type conductivity body as N+ type conductivity regions. With a p-channel MOSFET, the body, or epitaxial layer, is of n-type conductivity and the source and drain regions are formed in the n-type conductivity body as P+ type conductivity regions. It has been suggested that the semiconductor body, or layer, be formed on an insulating substrate, or over an insulation layer formed in a semiconductor substrate. Such technology sometimes is referred to as Silicon-on-Insulator (SOI) technology. Silicon-on-Insulator MOS technologies have a number of advantages over bulk silicon MOS transistors. These advantages include: reduced source/drain capacitance and hence improved speed performance at higher-operating frequencies; reduced N+ to P+ spacing and hence higher packing density due to ease of isolation; and higher xe2x80x9csoft errorxe2x80x9d upset immunity (i e., the immunity to the effects of alpha particle strikes).
Silicon-on-Insulator technology is characterized by the formation of a thin silicon layer for formation of the active devices over an insulating layer, such as an oxide, which is in turn formed over a substrate. Transistor sources in drains are formed by, for example, implantations into the silicon layer while transistor gates are formed by forming a patterned oxide and conductor (e.g. metal) layer structure. Such structures provide a significant gain in performance by having lower parasitic capacitance (due to the insulator layer) and increased drain current due to floating body charging effects (since no connection is made to the channel region and charging of the floating body provides access towards a majority of carriers which dynamically lower the threshold voltage, resulting in increased drain current). However, the floating body can introduce dynamic instabilities in the operation of such a transistor.
An SOI field effect transistor combines two separated immunity groups, generally formed by implantation, constituting the source and drain of the transistor with the general region (device body) between them covered by a thin gate insulator and a conductive gate. Typically no electrical connection is made to the channel region and therefore the body is electrically floating. Because the source and drain regions normally extend entirely through the thin silicon layer, the electrical potential of the body is governed by Kirchoffs current law, wherein the sum of the currents flowing into the body equals the sum of the currents flowing out of the body. Because the channel potential is dependent on the body voltage, the device threshold voltage varies as a function of the body voltage.
The boundaries between the channel region and the source and drain, respectively, form junctions which are normally reversed biased. Conduction in the channel region normally occurs immediately below the gate insulator in the region in which depletion can be controlled by a gate voltage. However, the junctions at the boundary of the source and drain also form a parasitic lateral bipolar transistor, which, in effect exists somewhat below the field effect transistor and may supplement desired channel current. On the other hand, the parasitic bipolar device cannot be controlled and under some bias conditions, the operation of the parasitic bipolar device may transiently dominate the operation of the field effect transistor and effectively occupy substantially the entire silicon layer at times when the channel current is not desired.
The parasitic bipolar transistor induces latch-up breakdown voltage and severely limits the maximum supply voltage at which SOI devices can operate. If the parasitic devices turn on, the SOI transistor cannot be switched by changing the gate bias. One approach for reducing the latch-up/breakdown effect have been based on reducing the electric field for a given drain bias (LDD approach). A method of implanting silicon impurity atoms such as argon, krypton or xenon has been employed to reduce the lifetime of minority carriers in the parasitic transistors, and hence reduce the gain of the parasitic transistors. This is known as implanting a minority carrier lifetime reducer (MCLR). Decreasing the lifetime of the junction minimizes the floating body effects by removing excess carriers, so that the carriers do not build up as fast in the body. As a result, the devices can be operated at a higher supply voltage resulting in improved performance.
Several limitations on miniaturization of field-effect transistors have been encountered. As a conduction channel is made small, several adverse effects on transistor performance occur such as series resistance and/or hot electron carrier effects.
The series resistance of an FET is a function of both the cross-sectional area and length of the conduction channel. It is desirable to limit the depth which the conduction channel extends into the substrate in order to limit the voltage which is needed to control the FET as well as to limit leakage and punch-through effects. However, the use of such shallow junctions causes the series resistance to increase. Series resistance must be maintained at a low value in order not to degrade the extrinsic transconductance of the FET. In general, the greater the extrinsic transconductance of the FET, the faster the circuit performance obtained. Low series resistance is often achieved by siliciding (i.e., forming a metal silicide at a metal-silicon interface) the source and drain or selectively depositing metal such as tungsten on the source and drain areas.
Conventionally, LDD, MCLR ion implantation and siliciding steps are all performed on a single device. However, conventional methods do not provide optimal results. In view of the above, it is apparent that there is a need in the art for a method of providing a device in which LDD, MCLR ion implantation and siliciding is performed such that better results as those available conventionally are achieved.
The present invention provides for a method for forming LDD regions, a silicide film layer and implanting a minority carrier lifetime reducer (MCLR) on a single device. Conventionally, MCLR implantation is performed prior to silicidation and after forming LDD regions. The MCLR implantation causes damage on the bottom edges of the source and drain, but due to the spacers being present fails to cause as much damage along the sidewalls, where the drain region and source region meet the body region and form parasitic transistors. In addition, the temperature annealing to form the silicide unanneals part of the damage caused by the MCLR implantation and as a result the MCLR implantation is not as effective. The present invention mitigates the aforementioned problems associated with conventional methods by performing a siliciding step prior to implanting the MCLR. In addition, after device formation, spacers used in forming drain and source regions are removed prior to step of implanting the MCLR implantation. The silicide acts as a natural mask and the step of implanting the MCLR implantation kills the lifetime along the sidewalls of the drain and source region.
Once aspect of the invention relates to a method of forming a MOSFET device. The method comprises the sequential steps of forming drain and source regions, forming at least one of a drain and source silicide film over at least one of the drain and source regions and forming at least one damaged sidewall region of the drain and source regions.
In another aspect of the invention, a method of forming an SOI NMOS transistor is provided. A SIMOX process is used to form a silicon base, an oxide layer between the base and a top silicon layer and an insulating oxide layer formed over the substrate. Nxe2x88x92 lightly doped source and drain extension regions are formed in the top silicon layer. Spacers are formed above the Nxe2x88x92 lightly doped source and drain extension regions. N+ source and N+ drain regions are formed in the top silicon layer, and at least one of a drain and source silicide film is formed over at least one of the drain and source regions. The spacers are removed and thereafter at least one damaged sidewall region of the drain and source regions is formed.
In yet another aspect of the invention, a method of forming a MOSFET device is provided. The method comprises the steps of forming Nxe2x88x92 lightly doped source and drain extension regions in the top silicon layer. Spacers are formed above the Nxe2x88x92 lightly doped source and drain extension regions. N+ source and N+ drain regions are formed in the top silicon layer and at least one of a drain and source silicide film is formed over at least one of the drain and source regions. The spacers are removed and thereafter at least one damaged sidewall region of the drain and source regions is formed.
In another aspect of the invention a MOSFET device is provided. The MOSFET device comprises a source region, a drain region, first lightly doped regions, the first lightly doped regions including a lightly doped source extension region and a lightly doped drain extension region and at least one damaged sidewall region at one of the source body junction and the drain body junction.
In yet another aspect of the invention a SOI NMOS device is provided. The SOI NMOS device comprises a silicon substrate and an insulating oxide layer formed over the substrate. A top silicon layer is formed over the insulating oxide layer and a gate formed over a portion of the top silicon layer. A gate oxide is formed between the gate and the top silicon layer. Nxe2x88x92 source and N+ drain regions are formed in the top silicon layer and Nxe2x88x92 lightly doped source and drain extension regions are formed in the top silicon layer. Source damaged regions and drain damaged regions are formed in sidewalls of the N+ source and N+ drain regions, respectively. Source silicide film and drain silicide film layers are formed over the N+ source and N+ drain regions, respectively. The source silicide film and drain silicide film layer facilitate mitigating series resistance in the source and drain regions and the source damaged regions and drain damaged regions facilitate mitigating floating body effects.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.